74LS194芯片設(shè)計VHDL代碼及Verilog代碼Quartus仿真

名稱：74LS194芯片設(shè)計VHDL代碼及Verilog代碼Quartus仿真

軟件：Quartus

語言：Verilog，VHDL

代碼功能：

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

設(shè)計文檔：

1. 工程文件

2. 程序文件

完整電路代碼

底層器件代碼(74LS194)

3. 程序編譯

整體統(tǒng)計報告

底層器件(74LS194)統(tǒng)計報告

4. RTL圖

5. 仿真圖

整體仿真圖

LS194模塊仿真圖(底層器件)

部分代碼展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
ENTITY?LS194?IS
???PORT?(
??????CP??:?IN?STD_LOGIC;
??????CR??:?IN?STD_LOGIC;
??????SL??:?IN?STD_LOGIC;
??????SR??:?IN?STD_LOGIC;
??????S0??:?IN?STD_LOGIC;
??????S1??:?IN?STD_LOGIC;
??????D0??:?IN?STD_LOGIC;
??????D1??:?IN?STD_LOGIC;
??????D2??:?IN?STD_LOGIC;
??????D3??:?IN?STD_LOGIC;
??????Q0??:?OUT?STD_LOGIC;
??????Q1??:?OUT?STD_LOGIC;
??????Q2??:?OUT?STD_LOGIC;
??????Q3??:?OUT?STD_LOGIC
???);
END?LS194;
ARCHITECTURE?behave?OF?LS194?IS
???SIGNAL?Q?:?STD_LOGIC_VECTOR(3?DOWNTO?0);
???SIGNAL?S?:?STD_LOGIC_VECTOR(1?DOWNTO?0);
BEGIN
???S?<=?(S1?&?S0);--合并為2bit
???
???PROCESS?(CP,?CR)
???BEGIN
??????IF?(CR?=?'0')?THEN
?????????Q?<=?"0000";
??????ELSIF?(CP'EVENT?AND?CP?=?'1')?THEN
?????????CASE?S?IS
????????????WHEN?"11"?=>--置數(shù)
???????????????Q?<=?(D0?&?D1?&?D2?&?D3);
????????????WHEN?"01"?=>--右移
???????????????Q(3)?<=?SR;
???????????????Q(2?DOWNTO?0)?<=?Q(3?DOWNTO?1);
????????????WHEN?"10"?=>--左移
???????????????Q(0)?<=?SL;
???????????????Q(3?DOWNTO?1)?<=?Q(2?DOWNTO?0);
????????????WHEN?"00"?=>--保持
???????????????Q?<=?Q;
?????????END?CASE;
??????END?IF;
???END?PROCESS;

點擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=537